ST STM32G0 1 Series User Manual

RM0444 Rev 5 261/1390
RM0444 System configuration controller (SYSCFG)
269
8.1.20 SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17)
Address offset: 0xC4
System reset value: 0x0000 0000
8.1.21 SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18)
Address offset: 0xC8
System reset value: 0x0000 0000
8.1.22 SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19)
Address offset: 0xCC
System reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM1
DAC
(1)
TIM6
(1)
rr r
1. Only significant on devices integrating TIM4, otherwise reserved. Refer to Section 1.4: Availability of peripherals.
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 LPTIM1: Low-power timer 1 interrupt request pending (EXTI line 29)
Bit 1 DAC: DAC underrun interrupt request pending
(1)
Bit 0 TIM6: Timer 6 interrupt request pending
(1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM2
TIM7
(1)
rr
1. Only significant on devices integrating TIM4, otherwise reserved. Refer to Section 1.4: Availability of peripherals.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 LPTIM2: Low-power timer 2 interrupt request pending (EXTI line 30)
Bit 0 TIM7: Timer 7 interrupt request pending
(1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
151413121110987654321 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM14
r

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English