ST STM32G0 1 Series - Figure 112. Counter Timing Diagram, Internal Clock Divided by 4; Figure 113. Counter Timing Diagram, Internal Clock Divided by N

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Advanced-control timer (TIM1) RM0444

534/1390 RM0444 Rev 5

Figure 112. Counter timing diagram, internal clock divided by 4

Figure 113. Counter timing diagram, internal clock divided by N

0000

0001

0000

MS31186V1

CK_PSC

Timerclock = CK_CNT

Counter register

Update event (UEV)

Counter underflow

Update interrupt flag

(UIF)

CNT_EN

001F20

MS31187V1