ST STM32G0 1 Series User Manual

RM0444 Rev 5 547/1390
RM0444 Advanced-control timer (TIM1)
624
Figure 131. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3)
1. OCxREF, where x is the rank of the complementary channel
Figure 132. Output stage of capture/compare channel (channel 4)
MS31199V2
Output
mode
controller
CNT>CCR1
CNT=CCR1
TIM1_CCMR1
OC1M[3:0]
OC1REF
OC1CE
Dead-time
generator
OC1_DT
OC1N_DT
DTG[7:0]
TIM1_BDTR
‘0’
‘0’
CC1E
TIM1_CCER
CC1NE
0
1
CC1P
TIM1_CCER
0
1
CC1NP
TIM1_CCER
OC1
Output
enable
circuit
OC1N
CC1E
TIM1_CCER
CC1NE
OSSI
TIM1_BDTR
MOE OSSR
0x
10
11
11
01
x0
Output
selector
OCxREF
OC1REFC
To the master mode
controller
Output
enable
circuit
0
1
OC5REF
(1)
ocref_clr_int
OCREF_CLR
ETRF
OCCS
TIMx_SMCR
OIS1N
TIM1_CR2
OIS1
MS33100V2
Output
mode
controller
CNT > CCR4
CNT = CCR4
TIM1_CCMR2
OC4M[3:0]
0
1
CC4P
TIM1_CCER
Output
enable
circuit
OC4
CC4E
TIM1_CCER
To the master
mode controller
OC4REF
OC4CE
0
1
CC4E
TIM1_CCER
‘0’
TIM1_BDTR
OSSI
MOE
OIS4
TIM1_CR2
0
1
ocref_clr_int
ETRF
OCREF_CLR
OCCS
TIMx_SMCR
Output
selector
OC3REF
OC4REFC

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English