ST STM32G0 1 Series

Extended interrupt and event controller (EXTI) RM0444
318/1390 RM0444 Rev 5
Figure 26. EXTI block diagram
EVG
Pulse
EXTI
Event
Trigger
Direct event(x) or
configurable event(y)
it_exti_per(y)*
c_event
Masking
events
Registers
AHB interface
PWR
CPU
rxev
Peripherals
sys_wakeup
Wakeup
Interrupt
Direct event(x)
c_evt_exti
c_evt_rst
hclk
c_fclk
c_wakeup
GPIO
Configurable event(15:0)
EXTImux
IOPort
exti[15:0]
To interconnect
* it_exti_per(y) are only available for configurable events (y)
MS44733V2
Table 59. EXTI signal overview
Signal name I/O Description
AHB interface I/O
EXTI register bus interface. When one event is configured to allow
security, the AHB interface support secure accesses
hclk I AHB bus clock and EXTI system clock
Configurable
event(y)
I
Asynchronous wakeup events from peripherals that do not have an
associated interrupt and flag in the peripheral
Direct event(x) I
Synchronous and asynchronous wakeup events from peripherals having
an associated interrupt and flag in the peripheral
IOPort(n) I GPIO ports[15:0]
exti[15:0] O EXTI output port to trigger other IPs
it_exti_per (y) O Interrupts to the CPU associated with configurable event (y)
c_evt_exti O High-level sensitive event output for CPU synchronous to hclk
c_evt_rst I Asynchronous reset input to clear c_evt_exti
sys_wakeup O Asynchronous system wakeup request to PWR for ck_sys and hclk
c_wakeup O Wakeup request to PWR for CPU, synchronous to hclk
Table 60. EVG pin overview
Pin name I/O Description
c_fclk I CPU free-running clock
c_evt_in I High-level sensitive event input from EXTI, asynchronous to CPU clock
c_event O Event pulse, synchronous to CPU clock
c_evt_rst O Event reset signal, synchronous to CPU clock