Advanced-control timer (TIM1) RM0444
584/1390 RM0444 Rev 5
21.4 TIM1 registers
Refer to for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
21.4.1 TIM1 control register 1 (TIM1_CR1)
Address offset: 0x00
Reset value: 0x0000
1514131211109876543210
Res. Res. Res. Res.
UIFRE
MAP
Res. CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN
rw rw rw rw rw rw rw rw rw rw rw
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 UIFREMAP: UIF status bit remapping
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (t
DTS
)used by the dead-time generators and the digital filters
(ETR, TIx):
00: t
DTS
=t
CK_INT
01: t
DTS
=2*t
CK_INT
10: t
DTS
=4*t
CK_INT
11: Reserved, do not program this value
Note: t
DTS
= 1/f
DTS
, t
CK_INT
= 1/f
CK_INT
.
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS[1:0]: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are
set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are
set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are
set both when the counter is counting up or down.
Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is
enabled (CEN=1) is not allowed
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