RM0444 Rev 5 189/1390
RM0444 Reset and clock control (RCC)
220
5.4.8 Clock interrupt clear register (RCC_CICR)
Address offset: 0x20
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 765432 1 0
Res. Res. Res. Res. Res. Res.
LSE
CSSC
CSSC Res. Res.
PLL
RDYC
HSE
RDYC
HSI
RDYC
HSI48
RDYC
LSE
RDYC
LSI
RDYC
w w wwww w w
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSC: LSE Clock security system interrupt clear
This bit is set by software to clear the LSECSSF flag.
0: No effect
1: Clear LSECSSF flag
Bit 8 CSSC: Clock security system interrupt clear
This bit is set by software to clear the HSECSSF flag.
0: No effect
1: Clear CSSF flag
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
Bit 4 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
Bit 3 HSIRDYC: HSI16 ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag
Bit 3 HSI48RDYC: HSI48 ready interrupt clear
This bit is set software to clear the HSI48RDYF flag.
0: No effect
1: Clear HSI48RDYF flag
Bit 1 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: Clear LSERDYF flag
Bit 0 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: Clear LSIRDYF flag
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