RM0444 Rev 5 217/1390
RM0444 Reset and clock control (RCC)
220
5.4.25 RCC register map
The following table gives the RCC register map and the reset values.
Bits 22:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: LSI oscillator ready
Set and cleared by hardware to indicate when the LSI oscillator is ready (stable):
0: Not ready
1: Ready
After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit
can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by
the Independent Watchdog or by the RTC.
Bit 0 LSION: LSI oscillator enable
Set and cleared by software to enable/disable the LSI oscillator:
0: Disable
1: Enable
Table 36. RCC register map and reset values
Off-
set
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
RCC_CR
Res.
Res.
Res.
Res.
Res.
Res.
PLLRDY
PLLON
HSI48RDY
HSI48ON
Res.
Res.
CSSON
HSEBYP
HSERDY
HSEON
Res.
Res.
HSIDIV[2:0]
HSIRDY
HSIKERON
HSION
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0000 0000 000101
0x04
RCC_ICSCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HSITRIM[6:0] HSICAL[7:0]
Reset value
1000000XXXXXXXX
0x08
RCC_CFGR
MCOPRE[3:0]
MCOSEL[3:0]
MCO2PRE[3:0]
MCO2SEL[3:0]
Res.
PPRE[2:0]
HPRE[3:0]
Res.
Res.
SWS[2:0]
SW[2:0]
Reset value
0000000000000000 0000000 000000
0x0C
RCC_PLL
CFGR
PLLR[2:0]
PLLREN
PLLQ[2:0]
PLLQEN
Res.
Res.
PLLP[4:0]
PLLPEN
Res.
PLLN[6:0]
Res.
PLLM
[2:0]
Res.
Res.
PLL
SRC
[1:0]
Reset value
00000000 000000 0010000 000 00
0x10 Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x14
RCC_CRRCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HSI48CAL[8:0]
Reset value
xxxxxxxxx
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