RM0444 Rev 5 205/1390
RM0444 Reset and clock control (RCC)
220
5.4.19 APB peripheral clock enable in Sleep/Stop mode register 1
(RCC_APBSMENR1)
Address offset: 0x4C
Reset value: 0b1111 1111 1111 1111 1111 1111 1011 0111
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 DMA2SMEN: DMA2 and DMAMUX clock enable during Sleep mode
(1)
Set and cleared by software.
0: Disable
1: Enable
Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is
enabled to at least one DMA peripheral.
Bit 0 DMA1SMEN: DMA1 and DMAMUX clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is
enabled to at least one DMA peripheral.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM
1SMEN
LPTIM
2
SMEN
DAC1
SME
N
(1)
PWR
SMEN
DBG
SMEN
UCPD
2
SMEN
(
1)
UCPD1
SMEN
(1)
CEC
SMEN
(1)
I2C3
SMEN
(1)
I2C2
SMEN
I2C1
SMEN
LP
UART
1
SMEN
USART4
SMEN
(1)
USART3
SMEN
(1)
USART2
SMEN
CRSS
MEN
(1
)
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
151413121110 9 8 7654 3 2 1 0
SPI3
SMEN
(1)
SPI2
SMEN
USB
SME
N
(1)
FDCA
N
SMEN
(1)
WWDG
SMEN
RTC
APB
SMEN
USART6
SMEN
(1)
USART5
SMEN
(1)
LP
UART
2
SMEN
(
1)
Res.
TIM7
SMEN
(1)
TIM6
SMEN
(1)
Res.
TIM4
SMEN
(1)
TIM3
SMEN
TIM2
SMEN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved with zero reset value. Refer to
Section 1.4: Availability of peripherals.
Bit 31 LPTIM1SMEN: Low Power Timer 1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 30 LPTIM2SMEN: Low Power Timer 2 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 29 DAC1SMEN: DAC1 interface clock enable during Sleep and Stop modes
(1)
Set and cleared by software.
0: Disable
1: Enable
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