ST STM32G0 1 Series

Reset and clock control (RCC) RM0444
206/1390 RM0444 Rev 5
Bit 28 PWRSMEN: Power interface clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 27 DBGSMEN: Debug support clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 26 UCPD2SMEN: UCPD2 clock enable during Sleep mode
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 25 UCPD1SMEN: UCPD1 clock enable during Sleep mode
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 24 CECSMEN: HDMI CEC clock enable during Sleep and Stop modes
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 23 I2C3SMEN: I2C3 clock enable during Sleep mode
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 22 I2C2SMEN: I2C2 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 21 I2C1SMEN: I2C1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 20 LPUART1SMEN: LPUART1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 19 USART4SMEN: USART4 clock enable during Sleep mode
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 18 USART3SMEN: USART3 clock enable during Sleep mode
(1)
Set and cleared by software.
0: Disable
1: Enable