ST STM32G0 1 Series User Manual

Nested vectored interrupt controller (NVIC) RM0444
314/1390 RM0444 Rev 5
12 Nested vectored interrupt controller (NVIC)
12.1 Main features
• 32 maskable interrupt channels (not including the sixteen Cortex
®
-M0+ interrupt lines)
• 4 programmable priority levels (2 bits of interrupt priority are used)
• Low-latency exception and interrupt handling
• Power management control
• Implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low-latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the programming manual PM0223.
12.2 SysTick calibration value register
The SysTick calibration value is set to 6500, which gives a reference time base of 1 ms with
the SysTick clock set to 6.5 MHz (max f
HCLK
/8).
12.3 Interrupt and exception vectors
Table 58 is the vector table. Information pertaining to a peripheral only applies to devices
containing that peripheral.
Table 58. Vector table
(1)
Position Priority
Type of
priority
Acronym Description Address
- - - - Reserved 0x0000_0000
- -3 fixed Reset Reset 0x0000_0004
- -2 fixed NMI_Handler
Non maskable interrupt. The SRAM
parity err., Flash ECC double err.,
HSE CSS and LSE CSS are linked
to the NMI vector.
0x0000_0008
- -1 fixed HardFault_Handler All class of fault 0x0000_000C
- - - - Reserved
0x0000_0010
0x0000_0014
0x0000_0018
0x0000_001C
0x0000_0020
0x0000_0024
0x0000_0028
- 3 settable SVC_Handler
System service call via SWI
instruction
0x0000_002C

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English