RM0444 Rev 5 259/1390
RM0444 System configuration controller (SYSCFG)
269
8.1.15 SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12)
Address offset: 0xB0
System reset value: 0x0000 0000
8.1.16 SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13)
Address offset: 0xB4
System reset value: 0x0000 0000
Bit 4 DMA1_CH7: DMA1 channel 7 interrupt request pending
(1)
Bit 3 DMA1_CH6 DMA1 channel 6 interrupt request pending
(1)
Bit 2 DMA1_CH5: DMA1 channel 5 interrupt request pending
Bit 1 DMA1_CH4: DMA1 channel 4 interrupt request pending
Bit 0 DMAMUX: DMAMUX interrupt request pending
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
COMP
3
(1)
COMP2
(1)
COMP1
(1)
ADC
rrrr
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 COMP3: Comparator 3 interrupt request pending (EXTI line 20)
(1)
Bit 2 COMP2: Comparator 2 interrupt request pending (EXTI line 18)
(1)
Bit 1 COMP1: Comparator 1 interrupt request pending (EXTI line 17)
(1)
Bit 0 ADC: ADC interrupt request pending
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TIM1_
BRK
TIM1_
UPD
TIM1_
TRG
TIM1_
CCU
rr r r
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 TIM1_BRK: Timer 1 break interrupt request pending
Bit 2 TIM1_UPD: Timer 1 update interrupt request pending
Bit 1 TIM1_TRG: Timer 1 trigger interrupt request pending
Bit 0 TIM1_CCU: Timer 1 commutation interrupt request pending
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