RM0444 Rev 5 215/1390
RM0444 Reset and clock control (RCC)
220
5.4.24 Control/status register (RCC_CSR)
Up to three wait states are inserted in case of successive accesses to this register. The
register is reset upon system reset, except for reset flags that are only reset upon power
reset.
Address: 0x60
Reset value: 0xXX00 0000
Bits 4:3 LSEDRV[1:0] LSE oscillator drive capability
Set by software to select the LSE oscillator drive capability as follows:
00: low driving capability
01: medium-low driving capability
10: medium-high driving capability
11: high driving capability
Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode.
Bit 2 LSEBYP: LSE oscillator bypass
Set and cleared by software to bypass the LSE oscillator (in debug mode).
0: Not bypassed
1: Bypassed
This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and
LSERDY=0).
Bit 1 LSERDY: LSE oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable):
0: Not ready
1: Ready
After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
Bit 0 LSEON: LSE oscillator enable
Set and cleared by software to enable LSE oscillator:
0: Disable
1: Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWR
RSTF
WWDG
RSTF
IWWG
RSTF
SFT
RSTF
PWR
RSTF
PIN
RSTF
OBL
RSTF
Res. RMVF Res. Res. Res. Res. Res. Res. Res.
r r rrrr r rw
1514131211109 8 7654321 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LSI
RDY
LSION
rrw
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