ST STM32G0 1 Series - Timx Counter [Alternate] (Timx_Cnt)(X = 2 to 4); Timx Prescaler (Timx_Psc)(X = 2 to 4)

General-purpose timers (TIM2/TIM3/TIM4) RM0444
688/1390 RM0444 Rev 5
Address offset: 0x24
Reset value: 0x0000 0000
22.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 4)
Bit 31 of this register has two possible definitions depending on the value of UIFREMAP in
TIMx_CR1 register:
• Previous section is for UIFREMAP = 0
• This section is for UIFREMAP = 1
Address offset: 0x24
Reset value: 0x0000 0000
22.4.14 TIMx prescaler (TIMx_PSC)(x = 2 to 4)
Address offset: 0x28
Reset value: 0x0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT[31:16]
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1514131211109876543210
CNT[15:0]
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Bits 31:16 CNT[31:16]: Most significant part counter value (TIM2)
Bits 15:0 CNT[15:0]: Least significant part of counter value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY CNT[30:16]
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1514131211109876543210
CNT[15:0]
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Bit 31 UIFCPY: UIF Copy
This bit is a read-only copy of the UIF bit of the TIMx_ISR register
Bits 30:16 CNT[30:16]: Most significant part counter value (TIM2)
Bits 15:0 CNT[15:0]: Least significant part of counter value
1514131211109876543210
PSC[15:0]
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