RM0444 Rev 5 433/1390
RM0444 Digital-to-analog converter (DAC)
441
16.7.13 DAC channel2 data output register (DAC_DOR2)
This register is available only on dual-channel DACs. Refer to Section 16.3: DAC
implementation.
Address offset: 0x30
Reset value: 0x0000 0000
16.7.14 DAC status register (DAC_SR)
Address offset: 0x34
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. DACC2DOR[11:0]
rrrrrrrrrrrr
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output
These bits are read-only, they contain data output for DAC channel2.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWST2
CAL_
FLAG2
DMAU
DR2
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rrrc_w1
1514131211109876543210
BWST1
CAL_
FLAG1
DMAU
DR1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rrrc_w1
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