Digital-to-analog converter (DAC) RM0444
434/1390 RM0444 Rev 5
Bit 31 BWST2: DAC channel2 busy writing sample time flag
This bit is systematically set just after Sample and hold mode enable. It is set each time the
software writes the register DAC_SHSR2, It is cleared by hardware when the write operation
of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).
0:There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written
1:There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written
Note: This bit is available only on dual-channel DACs. Refer to Section 16.3: DAC
implementation.
Bit 30 CAL_FLAG2: DAC channel2 calibration offset status
This bit is set and cleared by hardware
0: calibration trimming value is lower than the offset correction value
1: calibration trimming value is equal or greater than the offset correction value
Note: This bit is available only on dual-channel DACs. Refer to Section 16.3: DAC
implementation.
Bit 29 DMAUDR2: DAC channel2 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel2
1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is
driving DAC channel2 conversion at a frequency higher than the DMA service capability
rate).
Note: This bit is available only on dual-channel DACs. Refer to Section 16.3: DAC
implementation.
Bit 28 Reserved, must be kept at reset value.
Bit 27 Reserved, must be kept at reset value.
Bits 26:16 Reserved, must be kept at reset value.
Bit 15 BWST1: DAC channel1 busy writing sample time flag
This bit is systematically set just after Sample and hold mode enable and is set each time the
software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of
DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization).
0:There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1:There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
Bit 14 CAL_FLAG1: DAC channel1 calibration offset status
This bit is set and cleared by hardware
0: calibration trimming value is lower than the offset correction value
1: calibration trimming value is equal or greater than the offset correction value
Bit 13 DMAUDR1: DAC channel1 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel1
1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is
driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
Bit 12 Reserved, must be kept at reset value.
Bit 11 Reserved, must be kept at reset value.
Bits 10:0 Reserved, must be kept at reset value.
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