RM0444 Rev 5 509/1390
RM0444 AES hardware accelerator (AES)
522
When the data transferring between AES and memory is managed by DMA, the CCF flag is
not relevant and can be ignored (left set) by software. It must only be cleared when
transiting back to data transferring managed by software. See Suspend/resume operations
in ECB/CBC modes in Section 20.4.8: AES basic chaining modes (ECB, CBC) as example.
20.4.17 AES error management
AES configuration can be changed at any moment by clearing the EN bit of the AES_CR
register.
Read error flag (RDERR)
Unexpected read attempt of the AES_DOUTR register sets the RDERR flag of the AES_SR
register, and returns zero.
RDERR is triggered during the computation phase or during the input phase.
Note: AES is not disabled upon a RDERR error detection and continues processing.
An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details,
refer to Section 20.5: AES interrupts.
The RDERR flag is cleared by setting the ERRIE bit of the AES_CR register.
Write error flag (WDERR)
Unexpected write attempt of the AES_DINR register sets the WRERR flag of the AES_SR
register, and has no effect on the AES_DINR register. The WRERR is triggered during the
computation phase or during the output phase.
Note: AES is not disabled after a WRERR error detection and continues processing.
An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details,
refer to Section 20.5: AES interrupts.
The WRERR flag is cleared by setting the ERRC bit of the AES_CR register.
20.5 AES interrupts
Individual maskable interrupt sources generated by the AES peripheral signal the following
events:
• computation completed
• read error
• write error
The individual sources are combined into the common interrupt signal aes_it that connects
to NVIC (nested vectored interrupt controller). Each can individually be enabled/disabled, by
setting/clearing the corresponding enable bit of the AES_CR register, and cleared by setting
the corresponding bit of the AES_CR register.
The status of each can be read from the AES_SR register.
Table 108 gives a summary of the interrupt sources, their event flags and enable bits.
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