RM0444 Rev 5 329/1390
RM0444 Extended interrupt and event controller (EXTI)
335
13.5.8 EXTI software interrupt event register 2 (EXTI_SWIER2)
Address offset: 0x030
Reset value: 0x0000 0000
Contains only register bits for configurable events.
13.5.9 EXTI rising edge pending register 2 (EXTI_RPR2)
Address offset: 0x034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8765432 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FT2 Res. Res.
rw
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 FT2: Falling trigger event configuration bit of configurable line 34
(1)
.
This bit enables/disables the falling edge trigger for the event and interrupt on the
corresponding line.
0: Disable
1: Enable
The FT2 bit is only available in STM32G0B1xx and STM32G0C1xx. This bit is reserved in all
the other devices.
Bits 1:0 Reserved, must be kept at reset value.
1. The configurable lines are edge triggered, no glitch must be generated on these inputs.
If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set.
Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 7654321 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWI2 Res. Res.
rw
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 SWI2: Software rising edge event trigger on line 34)
Setting of any bit by software triggers a rising edge event on the line 34, resulting in an
interrupt, independently of EXTI_RTSR2 and EXTI_FTSR2 settings. This bit is automatically
cleared by hardware. Reading the bit always returns 0.
0: No effect
1: Rising edge event generated on the corresponding line, followed by an interrupt
The SWI2 bit is only available in STM32G0B1xx and STM32G0C1xx. This bit is reserved in
all the other devices.
Bits 1:0 Reserved, must be kept at reset value.
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