ST STM32G0 1 Series User Manual

System configuration controller (SYSCFG) RM0444
260/1390 RM0444 Rev 5
8.1.17 SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14)
Address offset: 0xB8
System reset value: 0x0000 0000
8.1.18 SYSCFG interrupt line 15 status register (SYSCFG_ITLINE15)
Address offset: BCh
System reset value: 0x0000 0000
8.1.19 SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16)
Address offset: 0xC0
System reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TIM1_
CC
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 TIM1_CC: Timer 1 capture compare interrupt request pending
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM2
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 TIM2: Timer 2 interrupt request pending
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TIM4
(1)
TIM3
rr
1. Only significant on devices integrating TIM4, otherwise reserved. Refer to Section 1.4: Availability of peripherals.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 TIM4: Timer 4 interrupt request pending
Bit 0 TIM3: Timer 3 interrupt request pending

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English