Interconnect matrix RM0444
272/1390 RM0444 Rev 5
Triggering signals
The output (from master) is on signal TIMx_TRGO (and TIMx_TRGOx), following a
configurable timer event.
With TIM14, TIM16, and TIM17 timers that do not have a trigger output, the output
compare 1 is used instead.
The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.
The input and output signals for TIM1 are shown in Figure 101: Advanced-control timer
block diagram.
The possible master/slave connections are given in Table 115: TIM1 internal trigger
connection and Table 126: TIMx Internal trigger connection.
Relevant power modes
These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.
9.3.2 From TIM1, TIM2, TIM3, TIM4, TIM6, TIM15, and EXTI, to ADC
Purpose
The general-purpose timers TIM2, TIM3, TIM4, and TIM15, basic timer TIM6, advanced-
control timer TIM1, and EXTI can be used to generate an ADC triggering event.
TIMx synchronization is described in: Section 21.3.27: ADC synchronization.
ADC synchronization is described in: Section 15.4: Conversion on external trigger and
trigger polarity (EXTSEL, EXTEN).
Triggering signals
The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.
The input (to ADC) is on signal EXT[15:0], JEXT[15:0].
The connection between timers and ADC is provided in Table 70: External triggers.
Relevant power modes
These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.
9.3.3 From ADC to TIM1
Purpose
ADC can provide trigger event through watchdog signals to the advanced-control timer
TIM1.
A description of the ADC analog watchdog setting is provided in: Section 15.7: Analog
window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR).
Trigger settings on the timer are provided in: Section 21.3.4: External trigger input.
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