ST STM32G0 1 Series User Manual

System configuration controller (SYSCFG) RM0444
248/1390 RM0444 Rev 5
8 System configuration controller (SYSCFG)
The devices feature a set of configuration registers. The main purposes of the system
configuration controller are the following:
• Enabling/disabling I
2
C Fast Mode Plus on some I/O ports
• Enabling/disabling the analog switch booster
• Configuring the IR modulation signal and its output polarity
• Remapping of some I/O ports
• Remapping the memory located at the beginning of the code area
• Flag pending interrupts from each interrupt line
• Managing robustness feature
8.1 SYSCFG registers
8.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1)
This register is used for specific configurations of memory and DMA requests remap and to
control special I/O features.
Two bits are used to configure the type of memory accessible at address 0x0000 0000.
These bits are used to select the physical remap by software and so, bypass the hardware
BOOT selection. After reset these bits take the value selected by the actual boot mode
configuration.
Address offset: 0x00
Reset value: 0x0000 000X (X is the memory mode selected by the actual boot mode
configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res.
I2C3_
FMP
(1)
I2C_
PA10_
FMP
I2C_
PA9_
FMP
I2C2_
FMP
I2C1_
FMP
I2C_
PB9_
FMP
I2C_
PB8_
FMP
I2C_
PB7_
FMP
I2C_
PB6_
FMP
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res.
UCPD2_
STROBE
(1)
UCPD1_
STROBE
(1)
BOOS
TEN
IR_MOD
[1:0]
IR_
POL
PA12_
RMP
PA11_
RMP
Res.
MEM_MODE
[1:0]
w w rw rw rw rw rw rw rw
1. Only significant on devices integrating the corresponding peripheral or function, otherwise reserved. Refer to Section 1.4:
Availability of peripherals.

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English