ST STM32G0 1 Series

Universal serial bus full-speed host/device interface (USB) RM0444
1262/1390 RM0444 Rev 5
37 Universal serial bus full-speed host/device interface
(USB)
37.1 Introduction
The USB peripheral implements an interface between a full-speed USB 2.0 bus and the
APB1 bus.
USB suspend/resume are supported, which permits to stop the device clocks for low-power
consumption.
37.2 USB main features
• USB specification version 2.0 full-speed compliant
• Supports both Host and Device modes
• Configurable number of endpoints from 1 to 8
• Dedicated packet buffer memory (SRAM) of 2048 bytes
• Cyclic redundancy check (CRC) generation/checking, Non-return-to-zero Inverted
(NRZI) encoding/decoding and bit-stuffing
• Isochronous transfers support
• Double-buffered bulk/isochronous endpoint/channel support
• USB Suspend/Resume operations
• Frame locked clock pulse generation
• USB 2.0 Link Power Management support (Device mode only)
• Battery Charging Specification Revision 1.2 support (Device mode only)
• USB connect / disconnect capability (controllable embedded pull-up resistor on
USB_DP line)
37.3 USB implementation
Table 216 describes the USB implementation in the devices.
Table 216. STM32G0x1 USB implementation
USB features
(1)
1. X= supported
USB
Host mode X
Number of endpoints 8
Size of dedicated packet buffer memory SRAM 2048 bytes
Dedicated packet buffer memory SRAM access scheme 32 bits
USB 2.0 Link Power Management (LPM) support in device X
Battery Charging Detection (BCD) support for device X
Embedded pull-up resistor on USB_DP line X