General-purpose I/Os (GPIO) RM0444
234/1390 RM0444 Rev 5
7.3.1 General-purpose I/O (GPIO)
During and just after reset, the alternate functions are not active and most of the I/O ports
are configured in analog mode.
The debug pins are in AF pull-up/pull-down after reset:
• PA14: SWCLK in pull-down
• PA13: SWDIO in pull-up
Note: PA14 is shared with BOOT0 functionality. Caution is required as the debugging device can
manipulate BOOT0 pin value.
Upon reset, the UCPD CCx lines present a pull-down resistor that can be disabled by
setting the UCPDx_STROBE bit of the SYSCFG_CFGR1 register.
When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.
7.3.2 I/O pin alternate function multiplexer and mapping
The device I/O pins are connected to on-board peripherals/modules through a multiplexer
that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals available on the same I/O pin.
00
x x x 0 0 Input Floating
x x x 0 1 Input PU
x x x 1 0 Input PD
x x x 1 1 Reserved (input floating)
11
x x x 0 0 Input/output Analog
xxx01
Reservedxxx10
xxx11
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate
function.
Table 42. Port bit configuration table
(1)
(continued)
MODE(i)
[1:0]
OTYPE(i)
OSPEED(i)
[1:0]
PUPD(i)
[1:0]
I/O configuration
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