Power control (PWR) RM0444
134/1390 RM0444 Rev 5
4.3.5 Low-power sleep mode (LP sleep)
Refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
I/O states in Low-power sleep mode
In Low-power sleep mode, all I/O pins keep the same state as in Run mode.
Entering Low-power sleep mode
The MCU enters Low-power sleep mode from Low-power run mode according to Entering
low-power modes, when the SLEEPDEEP bit in the Cortex
®
-M0+ System Control register is
clear.
Refer to Table 29: Low-power sleep mode summary for details on how to enter Low-power
sleep mode.
Exiting Low-power sleep mode
The MCU exits Low-power sleep mode according to Exiting low-power modes. When exiting
Low-power sleep mode by issuing an interrupt or an event, the MCU is in Low-power run
mode.
Refer to Table 29: Low-power sleep mode summary for details on how to exit Low-power
sleep mode.
Mode exit
If WFI or return from ISR was used for entry
Interrupt: refer to Table 58: Vector table
If WFE was used for entry and SEVONPEND = 0:
Wakeup event: refer to Section 13.3.2: EXTI direct event input wakeup
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 58: Vector table or
Wakeup event: refer to Section 13.3.2: EXTI direct event input wakeup
Wakeup latency None
Table 28. Sleep mode summary (continued)
Characteristic Description
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