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General-purpose timers (TIM14) RM0444

732/1390 RM0444 Rev 5

24.4.4 TIM14 event generation register (TIM14_EGR)

Address offset: 0x14

Reset value: 0x0000

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 CC1OF: Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input

capture mode. It is cleared by software by writing it to ‘0’.

0: No overcapture has been detected.

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was

already set

Bits 8:2 Reserved, must be kept at reset value.

Bit 1 CC1IF: Capture/compare 1 interrupt flag

This flag is set by hardware. It is cleared by software (input capture or output compare mode)

or by reading the TIMx_CCR1 register (input capture mode only).

0: No compare match / No input capture occurred

1: A compare match or an input capture occurred.

If channel CC1 is configured as output: this flag is set when he content of the counter

TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of

TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the

counter overflow (in up-counting and up/down-counting modes) or underflow (in down-

counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to

the CMS bits in the TIMx_CR1 register for the full description.

If channel CC1 is configured as input: this bit is set when counter value has been

captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge

sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).

Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow and if UDIS=’0’ in the TIMx_CR1 register.

– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if

URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1G UG

ST STM32G0 1 Series User Manual

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