RM0444 Rev 5 1257/1390
RM0444 FD controller area network (FDCAN)
1261
36.4.37 FDCAN CFG clock divider register (FDCAN_CKDIV)
Address offset: 0x0100
Reset value: 0x0000 0000
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 EFAI[1:0]: Event FIFO acknowledge index
After the Host has read an element or a sequence of elements from the Tx event FIFO, it has
to write the index of the last element read from Tx event FIFO to EFAI. This sets the Tx event
FIFO get index TXEFS[EFGI] to EFAI + 1 and updates the FIFO 0 fill level TXEFS[EFFL].
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PDIV[3:0]
rw rw rw rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 PDIV[3:0]: input clock divider
The APB clock could be divided prior to be used by the CAN sub system. The rate must be
computed using the divider output clock.
0000: Divide by 1
0001: Divide by 2
0010: Divide by 4
0011: Divide by 6
0100: Divide by 8
0101: Divide by 10
0110: Divide by 12
0111: Divide by 14
1000: Divide by 16
1001: Divide by 18
1010: Divide by 20
1011: Divide by 22
1100: Divide by 24
1101: Divide by 26
1110: Divide by 28
1111: Divide by 30
These are protected write (P) bits, which means that write access by the bits is possible only
when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
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