Tamper and backup registers (TAMP) RM0444
918/1390 RM0444 Rev 5
31.6.1 TAMP control register 1 (TAMP_CR1)
Address offset: 0x00
Backup domain reset value: 0xFFFF 0000
System reset: not affected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ITAMP6
E
ITAMP5
E
ITAMP4
E
ITAMP3
E
Res. Res.
rw
rw
rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TAMP3
E
TAMP2
E
TAMP1
E
rw
rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.
Bit 21 ITAMP6E: Internal tamper 6 enable: ST manufacturer readout
0: Internal tamper 6 disabled.
1: Internal tamper 6 enabled: a tamper is generated in case of ST manufacturer readout.
Bit 20 ITAMP5E: Internal tamper 5 enable: RTC calendar overflow
0: Internal tamper 5 disabled.
1: Internal tamper 5 enabled: a tamper is generated when the RTC calendar reaches its
maximum value, on the 31
st
of December 99, at 23:59:59. The calendar is then frozen and
cannot overflow.
Bit 19 ITAMP4E: Internal tamper 4 enable: HSE monitoring
0: Internal tamper 4 disabled.
1: Internal tamper 4 enabled. a tamper is generated when the HSE frequency is below or
above thresholds.
Bit 18 ITAMP3E: Internal tamper 3 enable: LSE monitoring
0: Internal tamper 3 disabled.
1: Internal tamper 3 enabled: a tamper is generated when the LSE frequency is below or
above thresholds.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
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