ST STM32G0 1 Series - Clock Selection; Figure 246. Update Rate Examples Depending on Mode and Timx

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General-purpose timers (TIM15/TIM16/TIM17) RM0444

752/1390 RM0444 Rev 5

Figure 246. Update rate examples depending on mode and TIMx_RCR register

settings

25.4.4 Clock selection

The counter clock can be provided by the following clock sources:

• Internal clock (CK_INT)

• External clock mode1: external input pin

• Internal trigger inputs (ITRx) (only for TIM15): using one timer as the prescaler for

another timer, for example, TIM1 can be configured to act as a prescaler for TIM15.

Refer to Using one timer as prescaler for another timer on page 664 for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000), then the CEN (in the TIMx_CR1

Edge-aligned mode

UEV

Update Event: preload registers transferred to active registers

and update interrupt generated.

Counter

TIMx_CNT

TIMx_RCR = 0 UEV

TIMx_RCR = 1 UEV

TIMx_RCR = 2 UEV

TIMx_RCR = 3 UEV

TIMx_RCR = 3

and

re-synchronization UEV

(by SW)

Upcounting

MS31084V2

ST STM32G0 1 Series - Clock Selection; Figure 246. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings