RM0444 Rev 5 327/1390
RM0444 Extended interrupt and event controller (EXTI)
335
13.5.5 EXTI falling edge pending register 1 (EXTI_FPR1)
Address offset: 0x010
Reset value: 0x0000 0000
Contains only register bits for configurable events.
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 RPIF20: Rising edge event pending for configurable line 20
(1)
.
This bit is set upon a rising edge event generated by hardware or by software (through the
EXTI_SWIER1 register) on the corresponding line. This bit is cleared by writing 1 into it.
0: No rising edge trigger request occurred
1: Rising edge trigger request occurred
The RPIF20 bit is only available in STM32G0B1xx and STM32G0C1xx. It is reserved in all
the other devices.
Bit 19 Reserved, must be kept at reset value.
Bits 18:0 RPIFx: Rising edge event pending for configurable line x (x = 18 to 0)
Each bit is set upon a rising edge event generated by hardware or by software (through the
EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0: No rising edge trigger request occurred
1: Rising edge trigger request occurred
The RPIF18 and RPIF17 bits are only available in STM32G071xx and STM32G081xx as
well as STM32G0B1xx and STM32G0C1xx. They are reserved in STM32G031xx and
STM32G041xx as well as STM32G051xx and STM32G061xx.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FPIF20 Res. FPIF18 FPIF17 FPIF16
rc_w1 rc_w1 rc_w1 rc_w1
1514131211109 8 7654321 0
FPIF15 FPIF14 FPIF13 FPIF12 FPIF11 FPIF10 FPIF9 FPIF8 FPIF7 FPIF6 FPIF5 FPIF4 FPIF3 FPIF2 FPIF1 FPIF0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:21 Reserved, must be kept at reset value.
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