RM0444 Rev 5 1265/1390
RM0444 Universal serial bus full-speed host/device interface (USB)
1307
charging capability (CDP or DCP cases in the standard), the host port is always presented
as a default standard data port (SDP).
Note: For LPM (link power management) this feature is not supported in Host mode.
37.4.1 Description of USB blocks used in both Device and Host modes
The USB peripheral implements all the features related to USB interfacing, which include
the following blocks:
• USB physical interface (USB PHY): this block is maintaining the electrical interface to
an external USB host. It contains the differential analog transceiver itself, controllable
embedded pull-up resistor (connected to USB_DP line) and support for battery
charging detection (BCD), multiplexed on same USB_DP and USB_DM lines. The
output enable control signal of the analog transceiver (active low) is provided externally
on USB_NOE. It can be used to drive some activity LED or to provide information about
the actual communication direction to some other circuitry.
• Serial interface engine (SIE): the functions of this block include: synchronization
pattern recognition, bit-stuffing, CRC generation and checking, PID
verification/generation, and handshake evaluation. It must interface with the USB
transceivers and uses the virtual buffers provided by the packet buffer interface for
local data storage. This unit also generates signals according to USB peripheral
events, such as start of frame (SOF), USB_Reset, data errors etc. and to endpoint
related events like end of transmission or correct reception of a packet; these signals
are then used to generate interrupts.
• Timer: this block generates a start-of-frame locked clock pulse and detects a global
suspend (from the host) when no traffic has been received for 3 ms.
• Packet buffer interface: this block manages the local memory implementing a set of
buffers in a flexible way, both for transmission and reception. It can choose the proper
buffer according to requests coming from the SIE and locate them in the memory
addresses pointed by the endpoint/channel registers. It increments the address after
each exchanged byte until the end of packet, keeping track of the number of
exchanged bytes and preventing the buffer to overrun the maximum capacity.
• Endpoint/channel-related registers: each endpoint/channel has an associated register
containing the endpoint/channel type and its current status. For mono-
directional/single-buffer endpoints, a single register can be used to implement two
distinct endpoints. The number of registers is 8, allowing up to 16 mono-
directional/single-buffer or up to 7 double-buffer endpoints in any combination. For
example the USB peripheral can be programmed to have 4 double buffer endpoints
and 8 single-buffer/mono-directional endpoints.
• Control registers: these are the registers containing information about the status of the
whole USB peripheral and used to force some USB events, such as resume and
power-down.
• Interrupt registers: these contain the interrupt masks and a re
cord of the events. They
can be used to inquire an interrupt reason, the interrupt status or to clear the status of a
pending interrupt.
Note: * Endpoint/channel 0 is always used for control transfer in single-buffer mode.
The USB peripheral is connected to the APB1 bus through an APB1 interface, containing
the following blocks:
• Packet memory: this is the local memory that physically contains the packet buffers. It
can be used by the packet buffer interface, which creates the data structure and can be
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