General-purpose timers (TIM15/TIM16/TIM17) RM0444
766/1390 RM0444 Rev 5
Figure 261. Break circuitry overview
1. Available on STM32G0B1xx and STM32G0C1xx salestypes only.
Caution: An asynchronous (clockless) operation is only guaranteed when the programmable filter is
disabled. If it is enabled, a fail safe clock mode (example, using the internal PLL and/or the
CSS) must be used to guarantee that break events are handled.
When a break occurs (selected level on the break input):
• The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or even releasing the control to the AFIO controller (selected by the OSSI bit). This
feature functions even if the MCU oscillator is off.
• Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control
(taken over by the AFIO controller) else the enable output remains high.
• When complementary outputs are used:
– The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.
– If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
MSv45736V3
COMP2 output
BKCMP2E
BKCMP2P
COMP1 output
BKCMP1E
BKCMP1P
BKIN inputs
from AF
controller
BKINE
BKINP
BKF[3:0]
Filter
BKP
Application break requests
ECC LOCK
Parity LOCK
PVD LOCK
Lockup LOCK
ECC Error
RAM parity Error
PVD
Core Lockup
CSS
SBIF flag
System break requests
Software break
requests: BG
BKE
BRK request
BIF flag
COMP3 output
(1)
BKCMP3E
BKCMP3P
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