RM0444 Rev 5 201/1390
RM0444 Reset and clock control (RCC)
220
5.4.16 APB peripheral clock enable register 2(RCC_APBENR2)
Address offset: 0x40
Reset value: 0x0000 0000
Bit 6 Reserved, must be kept at reset value.
Bit 5 TIM7EN: TIM7 timer clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 4 TIM6EN: TIM6 timer clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 2 TIM4EN: TIM4 timer clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 1 TIM3EN: TIM3 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 0 TIM2EN: TIM2 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ADC
EN
Res.
TIM17
EN
TIM16
EN
TIM15
EN
(1)
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIM14
EN
USART1
EN
Res.
SPI1
EN
TIM1
EN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SYS
CFG
EN
rw rw rw rw rw
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 ADCEN: ADC clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 19 Reserved, must be kept at reset value.
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