ST STM32G0 1 Series

Reset and clock control (RCC) RM0444
200/1390 RM0444 Rev 5
Bit 17 USART2EN: USART2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 16 CRSEN: CRS clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 15 SPI3EN: SPI3 clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 13 USBEN: USB clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 12 FDCANEN: FDCAN clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 11 WWDGEN: WWDG clock enable
Set by software to enable the window watchdog clock. Cleared by hardware system
reset
0: Disable
1: Enable
This bit can also be set by hardware if the WWDG_SW option bit is 0.
Bit 10 RTCAPBEN: RTC APB clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 9 USART6EN: USART6 clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 8 USART5EN: USART5 clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 7 LPUART2EN: LPUART2 clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable