ST STM32G0 1 Series - Page 199

RM0444 Rev 5 199/1390
RM0444 Reset and clock control (RCC)
220
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 27 DBGEN: Debug support clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 26 UCPD2EN: UCPD2 clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 25 UCPD1EN: UCPD1 clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 24 CECEN: HDMI CEC clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 23 I2C3EN: I2C3 clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 20 LPUART1EN: LPUART1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 19 USART4EN: USART4 clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 18 USART3EN: USART3 clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable