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RM0444 Rev 5 399/1390

RM0444 Analog-to-digital converter (ADC)

403

15.12.13 ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR)

Address offset: 0xA0

Reset value: 0x0000 0000

15.12.14 ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR)

Address offset: 0xA4

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

AWD2

CH18

AWD2

CH17

AWD2

CH16

rw rw rw

1514131211109876543210

AWD2

CH15

AWD2

CH14

AWD2

CH13

AWD2

CH12

AWD2

CH11

AWD2

CH10

AWD2

CH9

AWD2

CH8

AWD2

CH7

AWD2

CH6

AWD2

CH5

AWD2

CH4

AWD2

CH3

AWD2

CH2

AWD2

CH1

AWD2

CH0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD2CH[18:0]: Analog watchdog channel selection

These bits are set and cleared by software. They enable and select the input channels to be guarded

by analog watchdog 2 (AWD2).

0: ADC analog channel-x is not monitored by AWD2

1: ADC analog channel-x is monitored by AWD2

Note: The channels selected through ADC_AWD2CR must be also configured into the

ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is

allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is

ongoing).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

AWD3

CH18

AWD3

CH17

AWD3

CH16

rw rw rw

1514131211109876543210

AWD3

CH15

AWD3

CH14

AWD3

CH13

AWD3

CH12

AWD3

CH11

AWD3

CH10

AWD3

CH9

AWD3

CH8

AWD3

CH7

AWD3

CH6

AWD3

CH5

AWD3

CH4

AWD3

CH3

AWD3

CH2

AWD3

CH1

AWD3

CH0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD3CH[18:0]: Analog watchdog channel selection

These bits are set and cleared by software. They enable and select the input channels to be guarded

by analog watchdog 3 (AWD3).

0: ADC analog channel-x is not monitored by AWD3

1: ADC analog channel-x is monitored by AWD3

Note: The channels selected through ADC_AWD3CR must be also configured into the

ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is

allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English

ST STM32G0 1 Series User Manual

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ST STM32G0 1 Series Specifications

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