USB Type-C™ / USB Power Delivery interface (UCPD) RM0444
1322/1390 RM0444 Rev 5
38.4.6 UCPD Type-C pull-ups (Rp) and pull-downs (Rd)
UCPD offers simple control of these resistors via ANAMODE and ANASUBMODE[1:0]. In
case only one of the CC lines is to be used, it is possible to optimize power consumption by
disabling control on one the other line, through the CCENABLE[1:0] bitfield.
When the MCU is unpowered, it still presents the “dead battery” Rd, provided that
UCPDx_DBCC1 and UCPDx_DBCC2 pins are each connected to UCPDx_CC1 and
UCPDx_CC2 pins respectively.
If dead battery behavior is not required (for example for source only products), then
UCPDx_DBCC1 and UCPDx_DBCC2 pins must both be tied to ground.
After power arrives and the MCU boots, the desired behavior (for example source) must be
programmed into ANAMODE and ANASUBMODE[1:0] before setting the UCPDx_STROBE
bits of the SYSCFG1_CFGR1 register to activate this behavior.
Use of Standby low-power mode is possible for sinks in the unattached state.
38.4.7 UCPD Type-C voltage monitoring and de-bouncing
For correct operation of the Type-C state machine and for detecting the cable orientation,
the CC1/2 lines must be monitored for voltage level, while ignoring fast events such as
peaks.
Thresholds between voltage levels on the CC1/2 lines are determined through PHY
threshold detector settings.
The TYPEC_VSTATE_CC1/2[1:0] bitfields reflect the CC1/2 line levels processed with a
hardware de-bouncing filter that suppresses high-speed line events such as peaks. The
PHYCCSEL bit selects the line, CC1 or CC2, to be used for Power Delivery signaling.
For minimizing the power consumption, it is recommended to use the polling method, with
the Type-C detectors only turned on for the instant of polling, rather than keeping the
Type-C detectors permanently on and wake the device up from Stop mode upon CC1/2 line
events.
38.4.8 UCPD fast role swap (FRS) signaling and detection
FRS signaling
The FRS condition (a pulse of a specific length), is generated upon setting the FRSTX bit.
For the duration of FRS condition, the I/O configured as UCPD_FRSTX (alternate function)
controls, with high level, the gate of an external NMOS transistor that pulls the active CC
line down.
FRS detection
FRS monitoring is enabled by setting the bit FRSRXEN, after writing PHYCCSEL that
selects the active CC line depending on the cable orientation detected.
38.4.9 UCPD DMA Interface
DMA is implemented in the UCPD and when it is enabled the byte-level interrupts to handle
USBPD1_TXDR and USBPD1_RXDR registers (Tx and Rx data register, each one byte)
are no longer needed.
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