RM0444 Rev 5 1331/1390
RM0444 USB Type-C™ / USB Power Delivery interface (UCPD)
1346
38.7.2 UCPD configuration register 2 (UCPD_CFGR2)
Address offset: 0x004
Reset value: 0x0000 0000
Configuration of the UCPD Rx signal filtering. Writing to this register is only effective when
UCPD is disabled (UCPDEN = 0).
38.7.3 UCPD configuration register 3 (UCPD_CFGR3)
Address offset: 0x008
Reset value: 0x0000 0000
Configuration of UCPD analog PHY trimming. Writing to this register is only effective when
UCPD is disabled (UCPDEN = 0). The trim values of all resistors are determined by
hardware until the first software write into the register is performed.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
WUPEN
FORCECLK
RXFILT2N3
RXFILTDIS
rw rw rw rw
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 WUPEN: Wakeup from Stop mode enable
Setting the bit enables the UCPD_ASYNC_INT signal.
0: Disable
1: Enable
Bit 2 FORCECLK: Force ClkReq clock request
0: Do not force clock request
1: Force clock request
Bit 1 RXFILT2N3: BMC decoder Rx pre-filter sampling method
Number of consistent consecutive samples before confirming a new value.
0: 3 samples
1: 2 samples
Bit 0 RXFILTDIS: BMC decoder Rx pre-filter enable
0: Enable
1: Disable
The sampling clock is that of the receiver (that is, after pre-scaler).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. TRIM2_NG_CC3A0[3:0] TRIM2_NG_CC1A5[4:0] TRIM2_NG_CCRPD[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. TRIM1_NG_CC3A0[3:0] TRIM1_NG_CC1A5[4:0] TRIM1_NG_CCRPD[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw
To Next Page
Loading...
Need help?
General
