RM0444 Rev 5 1283/1390
RM0444 Universal serial bus full-speed host/device interface (USB)
1307
37.6 USB and USB SRAM registers
The USB peripheral registers can be divided into the following groups:
• Common registers: interrupt and control registers
• endpoint/channel registers: endpoint/channel configuration and status
The USB SRAM registers cover:
• Buffer descriptor table: location of packet memory used to locate data buffers (see
Section 2.2: Memory organization to find USB SRAM base address).
All register addresses are expressed as offsets with respect to the USB peripheral registers
base address, except the buffer descriptor table locations, which starts at the USB SRAM
base address.
Refer to Section 1.2 on page 53 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by words (32-bit).
37.6.1 Common registers
These registers affect the general behavior of the USB peripheral defining operating mode,
interrupt handling, device address and giving access to the current frame number updated
by the host PC.
USB control register (USB_CNTR)
Address offset: 0x40
Reset value: 0x0000 0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HOST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
THR
512M
rw rw
1514131211109876543210
CTRM
PMA
OVRM
ERRM
WKUP
M
SUSP
M
RST_D
CONM
SOFM
ESOF
M
L1REQ
M
Res.
L1RE
S
L2RE
S
SUS
PEN
SUSP
RDY
PDWN
USB
RST
rw rw rw rw rw rw rw rw rw rw rw rw r rw rw
Bit 31 HOST: HOST mode
HOST bit selects betweens host or device USB mode of operation. It must be set before
enabling the USB peripheral by the function enable bit.
0: USB Device function
1: USB host function
Bits 30:17 Reserved, must be kept at reset value.
Bit 16 THR512M: 512 byte threshold interrupt mask
0: 512 byte threshold interrupt disabled
1: 512 byte threshold interrupt enabled
Bit 15 CTRM: Correct transfer interrupt mask
0: Correct transfer (CTR) interrupt disabled.
1: CTR interrupt enabled, an interrupt request is generated when the corresponding bit in the
USB_ISTR register is set.
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