General-purpose timers (TIM2/TIM3/TIM4) RM0444
694/1390 RM0444 Rev 5
22.4.24 TIM4 option register 1 (TIM4_OR1)
Address offset: 0x50
Reset value: 0x0000 0000
22.4.25 TIM2 alternate function option register 1 (TIM2_AF1)
Address offset: 0x60
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
OCREF_CLR
[1:0]
rw rw
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 OCREF_CLR[1:0]: Ocref_clr source selection
This bit selects the ocref_clr input source.
Bits 1:0 OCREF_CLR[1:0]
00: COMP1 output is connected to the OCREF_CLR input
01: COMP2 output is connected to the OCREF_CLR input
10: COMP3
(1)
output is connected to the OCREF_CLR input
11: Reserved
1. COMP3 is available on STM32G0B1xx and STM32G0C1xx salestypes only.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2]
rw rw
1514131211109876543210
ETRSEL[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:14 ETRSEL[3:0]: ETR source selection
These bits select the ETR input source.
0000: ETR legacy mode
0001: COMP1
0010: COMP2
0011: LSE
0100: MCO
(1)
0101: MCO2
(1)
0110: COMP3
(1)
Others: Reserved
Bits 13:0 Reserved, must be kept at reset value.
1. Available onSTM32G0B1xx and STM32G0C1xx salestypes only.
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