ST STM32G0 1 Series User Manual

RM0444 Rev 5 263/1390
RM0444 System configuration controller (SYSCFG)
269
8.1.26 SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23)
Address offset: 0xDC
System reset value: 0x0000 0000
8.1.27 SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24)
Address offset: 0xE0
System reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FDCAN
2_IT0
(1)
FDCAN
1_IT0
(1)
TIM17
rr r
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
Bits 31:1 Reserved, must be kept at reset value.
Bit 2 FDCAN2_IT1: FDCAN2 interrupt request pending
(1)
Bit 1 FDCAN1_IT1: FDCAN1 interrupt request pending
(1)
Bit 0 TIM17: Timer 17 interrupt request pending
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. I2C1
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 I2C1: I2C1 interrupt request pending, combined with EXTI line 23
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
I2C3
(1)
I2C2
rr
1. Only significant on devices integrating I2C3, otherwise reserved. Refer to Section 1.4: Availability of peripherals.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 I2C3: I2C3 interrupt request pending (EXTI line 22)
(1)
Bit 0 I2C2: I2C2 interrupt request pending

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English