RM0444 Rev 5 1139/1390
RM0444 Serial peripheral interface / integrated interchip sound (SPI/I2S)
1195
35 Serial peripheral interface / integrated interchip
sound (SPI/I2S)
35.1 Introduction
The SPI/I²S interface can be used to communicate with external devices using the SPI
protocol or the I
2
S audio protocol. SPI or I
2
S mode is selectable by software. SPI Motorola
mode is selected by default after a device reset.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex
synchronous, serial communication with external devices. The interface can be configured
as master and in this case it provides the communication clock (SCK) to the external slave
device. The interface is also capable of operating in multimaster configuration.
The integrated interchip sound (I
2
S) protocol is also a synchronous serial communication
interface.It can operate in slave or master mode with half-duplex communication. It can
address four different audio standards including the Philips I
2
S standard, the MSB- and
LSB-justified standards and the PCM standard.
35.2 SPI main features
• Master or slave operation
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 4 to 16-bit data size selection
• Multimaster mode capability
• 8 master mode baud rate prescalers up to f
PCLK
/2
• Slave mode frequency up to f
PCLK
/2.
• NSS management by hardware or software for both master and slave: dynamic change
of master/slave operations
• Programmable clock polarity and phase
• Programmable data order with MSB-first or LSB-first shifting
• Dedicated transmission and reception flags with interrupt capability
• SPI bus busy status flag
• SPI Motorola support
• Hardware CRC feature for reliable communication:
– CRC value can be transmitted as last byte in Tx mode
– Automatic CRC error checking for last received byte
• Master mode fault, overrun flags with interrupt capability
• CRC Error flag
• Two 32-bit embedded Rx and Tx FIFOs with DMA capability
• Enhanced TI and NSS pulse modes support
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