Reset and clock control (RCC) RM0444
180/1390 RM0444 Rev 5
5.4.2 Internal clock source calibration register (RCC_ICSCR)
Address offset: 0x04
Reset value: 0x0000 40XX, where X is factory-programmed.
5.4.3 Clock configuration register (RCC_CFGR)
One or two wait states are inserted if this register is accessed during clock source switch,
and between zero and 15 wait states are inserted if during an update of APB or AHB
prescaler values.
Address offset: 0x08
Reset value: 0x0000 0000
Bit 8 HSION: HSI16 clock enable
Set and cleared by software.
Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown
mode.
Forced by hardware to keep the HSI16 oscillator ON when it is used directly or indirectly as
system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of
the HSE oscillator used for system clock).
0: HSI16 oscillator OFF
1: HSI16 oscillator ON
Bits 7:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 765432 1 0
Res. HSITRIM[6:0] HSICAL[7:0]
rwrwrwrwrwrwrwrrrrrr r r
Bits 31:15 Reserved, must be kept at reset value.
Bits 14:8 HSITRIM[6:0]: HSI16 clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the HSI16 clock.
The default value is 64, which, when added to the HSICAL value, trims the HSI16 to 16 MHz
± 1 %.
Bits 7:0 HSICAL[7:0]: HSI16 clock calibration
These bits are initialized at startup with the factory-programmed HSI16 calibration trim value.
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim
value. Refer to DS for the trimming steps granularity. The frequency progression presents
discontinuities when HSICAL crosses multiples of 64.
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