ST STM32G0 1 Series

FD controller area network (FDCAN) RM0444
1248/1390 RM0444 Rev 5
36.4.22 FDCAN Rx FIFO 0 status register (FDCAN_RXF0S)
Address offset: 0x0090
Reset value: 0x0000 0000
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 FLST: Filter list
Indicates the filter list of the matching filter element.
0: Standard filter list
1: Extended filter list
Bits 14:13 Reserved, must be kept at reset value.
Bits 12:8 FIDX[4:0]: Filter index
Index of matching filter element. Range is 0 to RXGFC[LSS] - 1 or RXGFC[LSE] - 1.
Bits 7:6 MSI[1:0]: Message storage indicator
00: No FIFO selected
01: FIFO overrun
10: Message stored in FIFO 0
11: Message stored in FIFO 1
Bits 5:3 Reserved, must be kept at reset value.
Bits 2:0 BIDX[2:0]: Buffer index
Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = 1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. RF0L F0F Res. Res. Res. Res. Res. Res. F0PI[1:0]
rr rr
1514131211109876543210
Res. Res. Res. Res. Res. Res. F0GI[1:0] Res. Res. Res. Res. F0FL[3:0]
rr rrrr
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 RF0L: Rx FIFO 0 message lost
This bit is a copy of interrupt flag IR[RF0L]. When IR[RF0L] is reset, this bit is also reset.
0: No Rx FIFO 0 message lost
1: Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0
Bit 24 F0F: Rx FIFO 0 full
0: Rx FIFO 0 not full
1: Rx FIFO 0 full
Bits 23:18 Reserved, must be kept at reset value.
Bits 17:16 F0PI[1:0]: Rx FIFO 0 put index
Rx FIFO 0 write index pointer, range 0 to 2.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 F0GI[1:0]: Rx FIFO 0 get index
Rx FIFO 0 read index pointer, range 0 to 2.