ST STM32G0 1 Series User Manual

RM0444 Rev 5 663/1390
RM0444 General-purpose timers (TIM2/TIM3/TIM4)
701
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Figure 203. Control circuit in external clock mode 2 + trigger mode
22.3.19 Timer synchronization
The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 204: Master/Slave timer example and Figure 205: Master/slave connection example
with 1 channel only timers present an overview of the trigger selection and the master mode
selection blocks.
Figure 204. Master/Slave timer example
MS33110V1
34 35 36
TIF
Counter register
Counter clock = CK_CNT = CK_PSC
ETR
CEN/CNT_EN
TI1
MSv62395V1
Master
mode
control
UEV
Clock
Prescaler Counter
Slave
mode
control
Prescaler Counter
CK_PSCITR2TRGO
MMS
SMS
TS
Input
trigger
selection
TIM3
TIM2

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English