ST STM32G0 1 Series - TIM15 DMA Control Register (TIM15_DCR); TIM15 DMA Address for Full Transfer (TIM15_DMAR)

RM0444 Rev 5 801/1390
RM0444 General-purpose timers (TIM15/TIM16/TIM17)
830
25.5.17 TIM15 DMA control register (TIM15_DCR)
Address offset: 0x48
Reset value: 0x0000
25.5.18 TIM15 DMA address for full transfer (TIM15_DMAR)
Address offset: 0x4C
Reset value: 0x0000
Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5] = 0xx => DT = DTG[7:0] x t
dtg
with t
dtg
= t
DTS
DTG[7:5] = 10x => DT = (64+DTG[5:0]) x t
dtg
with t
dtg
= 2 x t
DTS
DTG[7:5] = 110 => DT = (32+DTG[4:0]) x t
dtg
with t
dtg
= 8 x t
DTS
DTG[7:5] = 111 => DT = (32+DTG[4:0]) x t
dtg
with t
dtg
= 16 x t
DTS
Example if t
DTS
= 125 ns (8 MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 µs to 31750 ns by 250 ns steps,
32 µs to 63 µs by 1 µs steps,
64 µs to 126 µs by 2 µs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
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Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0]
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Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bit field defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
1514131211109876543210
DMAB[15:0]
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