ST STM32G0 1 Series - DAC Sample and Hold Time Register (DAC_SHHR); DAC Sample and Hold Refresh Time Register (DAC_SHRR)

Digital-to-analog converter (DAC) RM0444
438/1390 RM0444 Rev 5
16.7.19 DAC sample and hold time register (DAC_SHHR)
Address offset: 0x48
Reset value: 0x0001 0001
Note: These bits can be written only when the DAC channel is disabled and in Normal operating
mode (when bit ENx=0 and bit CENx=0 in the DAC_CR register). If ENx=1 or CENx=1 the
write operation is ignored.
16.7.20 DAC sample and hold refresh time register (DAC_SHRR)
Address offset: 0x4C
Reset value: 0x0001 0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. THOLD2[9:0]
rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. THOLD1[9:0]
rw rw rw rw rw rw rw rw rw rw
Bits 31:26
Reserved, must be kept at reset value.
Bits 25:16 THOLD2[9:0]: DAC channel2 hold time (only valid in Sample and hold mode).
Hold time= (THOLD[9:0]) x LSI clock period
Note: This register can be modified only when EN2=0.
These bits are available only on dual-channel DACs. Refer to Section 16.3: DAC
implementation.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:0 THOLD1[9:0]: DAC channel1 hold time (only valid in Sample and hold mode)
Hold time= (THOLD[9:0]) x LSI clock period
Note: This register can be modified only when EN1=0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. TREFRESH2[7:0]
rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. TREFRESH1[7:0]
rw rw rw rw rw rw rw rw