RM0444 Rev 5 187/1390
RM0444 Reset and clock control (RCC)
220
5.4.7 Clock interrupt flag register (RCC_CIFR)
Address offset: 0x1C
Reset value: 0x0000 0000
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock:
0: Disable
1: Enable
Bit 4 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization:
0: Disable
1: Enable
Bit 3 HSIRDYIE: HSI16 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator
stabilization:
0: Disable
1: Enable
Bit 2 HSI48RDYIE: HSI48 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator
stabilization:
0: Disable
1: Enable
Bit 1 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization:
0: Disable
1: Enable
Bit 0 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator
stabilization:
0: Disable
1: Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 765432 1 0
Res. Res. Res. Res. Res. Res.
LSE
CSSF
CSSF Res. Res.
PLL
RDYF
HSE
RDYF
HSI
RDYF
HSI48
RDYF
LSE
RDYF
LSI
RDYF
r r rrrr r r
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