ST STM32G0 1 Series - Figure 236. TIM15 Block Diagram

RM0444 Rev 5 743/1390
RM0444 General-purpose timers (TIM15/TIM16/TIM17)
830
Figure 236. TIM15 block diagram
1. The internal break event source can be:
- A clock failure event generated by CSS. For further information on the CSS, refer to Section 5.2.9: Clock security system
(CSS)
- A PVD output
- SRAM parity error signal
- Cortex
®
-M0+ LOCKUP (Hardfault) output
- COMP output
MSv40934V5
U
U
U
CC1I
CC2I
Trigger
controller
+/-
Stop, clear or up/down
TI1FP1
TI2FP2
ITR0
ITR1
ITR2
TRGI
Output
control
DTG
TRGO
OC1REF
OC2REF
REP register
U
Repetition
counter
UI
Reset, enable, count
CK_PSC
IC1
IC2
IC2PS
IC1PS
TI1FP1
TRG
TRC
TRC
ITR
TRC
TI1F_ED
CC1I
CC2I
TI1FP2
TI2FP1
TI2FP2
TI1
TI2
TIMx_CH1
TIMx_CH2
OC1
OC2
TIMx_CH1
TIMx_CH2
TIMx_CH1N
OC1N
to other timers
Slave
controller
mode
PSC
prescaler
CNT counter
Internal clock (CK_INT) from RCC
CK_CNT
ITR3
DTG registers
Capture/Compare 1 register
Notes:
Reg
Preload registers transferred
to active registers on U event
according to control bit
Event
Interrupt & DMA output
TIMx_BKIN
Internal sources
SBIF
Auto-reload register
Capture/Compare 2 register
Prescaler
Prescaler
XOR
Output
control
Input
filter &
edge
detector
Break circuitry
(1)
BIF
BRK request
TI1[1..15]
TI1[0]
Input
filter &
edge
detector
TI2[1..15]
TI2[0]
(1)