FD controller area network (FDCAN) RM0444
1256/1390 RM0444 Rev 5
36.4.35 FDCAN Tx event FIFO status register (FDCAN_TXEFS)
Address offset: 0x00E4
Reset value: 0x0000 0000
36.4.36 FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA)
Address offset: 0x00E8
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. TEFL EFF Res. Res. Res. Res. Res. Res. EFPI[1:0]
rr rr
1514131211109876543210
Res. Res. Res. Res. Res. Res. EFGI[1:0] Res. Res. Res. Res. Res. EFFL[2:0]
rr rrr
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 TEFL: Tx Event FIFO element lost
This bit is a copy of interrupt flag IR[TEFL]. When IR[TEFL] is reset, this bit is also reset.
0 No Tx event FIFO element lost
1 Tx event FIFO element lost, also set after write attempt to Tx Event FIFO of size 0.
Bit 24 EFF: Event FIFO full
0: Tx event FIFO not full
1: Tx event FIFO full
Bits 23:18 Reserved, must be kept at reset value.
Bits 17:16 EFPI[1:0]: Event FIFO put index
Tx Event FIFO write index pointer, range 0 to 3.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 EFGI[1:0]: Event FIFO get index
Tx Event FIFO read index pointer, range 0 to 3.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 EFFL[2:0]: Event FIFO fill level
Number of elements stored in Tx event FIFO, range 0 to 3.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EFAI[1:0]
rw rw
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