Digital-to-analog converter (DAC) RM0444
428/1390 RM0444 Rev 5
16.7.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1)
Address offset: 0x08
Reset value: 0x0000 0000
16.7.4 DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1)
Address offset: 0x0C
Reset value: 0x0000 0000
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 SWTRIG2: DAC channel2 software trigger
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR2
register value has been loaded into the DAC_DOR2 register.
This bit is available only on dual-channel DACs. Refer to Section 16.3: DAC
implementation.
Bit 0 SWTRIG1: DAC channel1 software trigger
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1
register value has been loaded into the DAC_DOR1 register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. DACC1DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software. They specify 12-bit data for DAC channel1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
DACC1DHR[11:0] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw
To Next Page
Loading...
Need help?
General
