RM0444 Rev 5 169/1390
RM0444 Reset and clock control (RCC)
220
For more details on how to measure the HSI16 frequency variation, refer to Section 5.2.16:
Internal/external clock measurement with TIM14/TIM16/TIM17.
The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI16 RC is stable
or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware.
The HSI16 RC can be switched on and off using the HSION bit in the Clock control register
(RCC_CR).
The HSI16 signal can also be used as a backup source (auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 5.2.9: Clock security system (CSS) on page 171.
5.2.3 HSI48 clock
Available on the STM32G0B1xx and STM32G0C1xx devices only, the HSI48 clock signal is
generated from an internal 48 MHz RC oscillator. It can be used as clock source for the USB
and RNG peripherals.
The internal 48MHz RC oscillator provides a high-precision clock to the USB peripheral
thanks to the clock recovery system (CRS). CRS uses the USB SOF signal, LSE clock or an
external signal as timing reference to precisely adjust the HSI48 RC oscillator frequency.
HSI48 RC oscillator is disabled as soon as the system enters in Stop or Standby mode.
When the CRS is not used, the HSI48 RC oscillator runs on its free-run frequency which is
subject to manufacturing process variations. The devices are factory-calibrated for ~3 %
accuracy at T
A
= 25°C.
Refer to CRS section for more details on how to configure and use CRS.
The HSI48RDY flag in the RCC_CR register indicates if HSI48 is stable or not. At startup,
the HSI48 clock is not released until this flag is set by hardware.
The HSI48 RC oscillator is enabled/disabled through the HSI48ON bit of the RCC_CR
register. It is automatically enabled (by hardware setting the HSI48ON bit) when selected as
clock source for the USB peripheral, as long as the USB peripheral is enabled.
Furthermore, it is possible to output the HSI48 clock through the MCO and MCO2
multiplexers and use it as a clock source for other application components.
5.2.4 PLL
The internal PLL multiplies the frequency of HSI16- or HSE-based clock fetched on its input,
to produce three independent clock outputs. The allowed input frequency range is from 2.66
to 16 MHz. The dedicated divider PLLM with division factor programmable from one to eight
allows setting a frequency within the valid PLL input range. Refer to Figure 10: Clock tree
and PLL configuration register (RCC_PLLCFGR).
The PLL configuration (selection of the input clock and multiplication factor) must be done
before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1. Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR).
2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
3. Change the desired parameter.
4. Enable the PLL again by setting PLLON to 1.
5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, and PLLREN in PLL
configuration register (RCC_PLLCFGR).
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